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How it works
Many times we think of memory in terms of a stack, a one-dimensional table. But when we get right down to the gritty details, it becomes a bit more complicated. In this lesson, our focus is on main memory, or more precisely, DRAM (Dynamic Random Access Memory). Since it is dynamic, DRAM needs to be refreshed every 8 milliseconds or so.
Think of a standard 4MB block of RAM. If the structure was laid out in one dimension, you would need a decoder that could handle 4 MILLION output lines. That does not sound efficient.
How it works
DRAM helps us out because it splits addresses into two pieces: a two-dimensional array or matrix. In this way, the number of address lines to process are drastically reduced, from 4 million down to 4096 (2048 per row; 2048 per column). In addition to DRAM, we have synchronous DRAM, or SDRAM, which also takes advantage of the two-dimensional array of memory.
SDRAM also has a better clock mechanism (better synchronization between main memory and the microprocessor clock), and programmers have more control of some technical elements such as ‘burst’ (which we will cover shortly).
Bits are stored in the array on the chip: there’s a row address decoder, a column address decoder, and sense amplifiers. Let’s look at the row and column access in more detail. Figure 1 shows a rough outline of the two-dimensional matrix of SDRAM:
When SDRAM is engaged, the first step of the computer is to set the bit lines to a known value, which is required for the next row access. Next, the row is accessed, followed by the column. The row access (RAS) decodes the address of the row and enables it. Finally, the column address (CAS) is decoded and a few of the sense amplifiers in the column are selected and read. This is where we gain efficiency.
During column access, the system has the ability to read multiple columns on the same row, WITHOUT having to look at another row. This is called burst mode and it greatly speeds up the memory access. Once the first bit is accessed, this process is quite rapid, but it is most effective if the bits are in sequence and in the same row (otherwise you’re jumping around and not gaining any efficiency).
SDRAM has some built in features to aid the burst mode process. Special registers called mode registers set the burst length, or the amount of synchronous data loaded to the bus. This register can be modified by a programmer to set the delay between reads and data transfers. Timing is everything. SDRAM has several components that impact the speed and timing of access and burst mode.
So far we’ve been talking about burst mode and 2D access on single processors. But what if you used multiple processors to access the same memory? In theory, this should drastically burst the bubble (pardon the pun) limiting our performance. Multi-access memory provides 2D access, but using multiple processors.
If you add more processing cores to your system, the 2D memory access should be much faster (assuming they do not collide with one another on the way to the same data). As long as there are no conflicts, where one processor is trying to access the same location as another, additional cores can help speed up the RAS and CAS operations. However, adding more cores will not necessarily provide any benefit.
Recall the timings for 2D access. Embedded in all of this is a computing overhead that you may not be able to overcome. Data transfer still takes time, especially when you have multiple cores. Throwing more hardware at the problem will not necessarily solve it.
DRAM (Dynamic Random Access Memory) and SDRAM (synchronous DRAM) can make use of two-dimensional memory. This means memory is arranged in a 2D matrix of rows and columns instead of a vertical stack. SDRAM handles this better since it has a better clock mechanism and provides control over some features. SDRAM employs burst mode which allows access to multiple columns on the same row. Mode registers set the burst length. Even though burst mode provides a performance boost, overhead still exists in terms of time and latency between events. Adding multiple processors can benefit 2D memory access, but can also introduce the risk of conflicts, e.g., two processors trying to update the same block.
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